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Shader authors can work around\nthis by explicitly tiling and staging through shared memory, but it is\ncumbersome. Similarly, for networks that need slightly larger matrices that\nshould still fit in the register file, they are again required to explicitly\ntile.",{"type":10,"tag":33,"props":39,"children":40},{},[41,43,49],{"type":15,"value":42},"Some networks require operations like reductions or matrix ",{"type":10,"tag":44,"props":45,"children":46},"em",{},[47],{"type":15,"value":48},"Use",{"type":15,"value":50}," conversions,\nand currently these require a round trip through shared memory.",{"type":10,"tag":33,"props":52,"children":53},{},[54],{"type":15,"value":55},"Simple row/col-major ordering is fine for 2D tensors, but many networks\nhave tensors with more dimensions, more complex slicing of tensors, and\npadding at tensor boundaries. VK_KHR_cooperative_matrix does not address\nthese use cases.",{"type":10,"tag":33,"props":57,"children":58},{},[59],{"type":15,"value":60},"Many large networks store weights in a quantized format, and there is not\na great way to dequantize these as they are loaded into a cooperative\nmatrix.",{"type":10,"tag":11,"props":62,"children":63},{},[64],{"type":15,"value":65},"Fortunately, VK_KHR_cooperative_matrix provides a solid foundation that we can\nextend to address all of these issues.",{"type":10,"tag":11,"props":67,"children":68},{},[69],{"type":15,"value":70},"We hope that this new functionality is useful both for handwritten shaders and\nas a target for graph compilers.",{"type":10,"tag":17,"props":72,"children":74},{"id":73},"_solution_space",[75],{"type":15,"value":76},"Solution Space",{"type":10,"tag":11,"props":78,"children":79},{},[80],{"type":15,"value":81},"This proposal includes several new features, each with their own solution\nspaces:",{"type":10,"tag":29,"props":83,"children":84},{},[85,90,101,106,111],{"type":10,"tag":33,"props":86,"children":87},{},[88],{"type":15,"value":89},"Compilers can easily scale matrix sizes by internally tiling them, and more\nflexible matrix dimensions are clearly valuable for ease of use. The main\nquestion is whether the sizes should be completely arbitrary, or defined as\na multiple of some minimum granularity. Completely arbitrary sizes might\nlead to unexpected complexity or performance issues, so for simplicity this\nextension adds minimum granularities, and any multiple is supported up to\nsome relatively large upper bound. Additionally, supporting matrices at\nworkgroup scope allows implementations to more efficiently support larger\nmatrix sizes, and to optimize their loads by automatically staging them\nthrough shared memory.",{"type":10,"tag":33,"props":91,"children":92},{},[93,95,99],{"type":15,"value":94},"Matrix ",{"type":10,"tag":44,"props":96,"children":97},{},[98],{"type":15,"value":48},{"type":15,"value":100}," conversions are important for writing fused network kernels,\nso that an accumulator can be used as an operand for another multiply.\nThe most important conversions seem to be Accumulator→A, and\nAccumulator→B with optional transpose. To minimize complexity, this is\nall that is supported for now.",{"type":10,"tag":33,"props":102,"children":103},{},[104],{"type":15,"value":105},"Reductions are common in networks, for example softmax activation requires\na reduction over rows, and max-pooling requires a reduction over 2x2\nneighborhoods. We support these in Accumulator matrices since that is the\nprimary place they are needed. It is also possible to do sum-reduce of a\nrow of an A matrix or a column of a B matrix by multiplying by a matrix\nof all ones, so we do not add an additional way to do this.",{"type":10,"tag":33,"props":107,"children":108},{},[109],{"type":15,"value":110},"The existing row/col-major pitch-based addressing only covers the simplest\nuse cases and misses a lot of real-world use cases, like slicing and\nreinterpreting views of tensors, and clamping/padding at tensor boundaries.\nWe considered fully programmable addressing (e.g. function pointer to\ncalculate addresses), but the generality makes it difficult for the\nimplementation to do optimizations like coalescing loads or staging through\nshared memory. The solution we settled on, tensor layouts and views, are\nconceptually similar to how tensors are handled in APIs like PyTorch, so\nit handles common use cases. The regular structure imposed by the tensor\nlayout aids the compiler in performing the aforementioned optimizations.\nAnd while the tensor layout and view calculations appear expensive in their\nfull generality, applications \"pay for what they use\" and the simpler cases\nare still pretty cheap.",{"type":10,"tag":33,"props":112,"children":113},{},[114],{"type":15,"value":115},"Quantized weights are often stored in sub-byte types (e.g. int4) or as part\nof a larger block, and need to be scaled and/or run through a lookup table\nto produce the dequantized value. Previously, this had to be done manually\nand copied into shared memory to be loaded into a matrix. We support block\ndimensions in the addressing calculations and a decode callback function that\nallows the values to be dequantized as they are loaded into the matrix.",{"type":10,"tag":17,"props":117,"children":119},{"id":118},"_proposal",[120],{"type":15,"value":121},"Proposal",{"type":10,"tag":11,"props":123,"children":124},{},[125],{"type":15,"value":126},"The solution space section describes all the separate features of the proposal\nand which solutions we have chosen. Then a final question is how to package these\nfeatures. Most of these can be used independently as incremental additions to\nVK_KHR_cooperative_matrix. These are specified as independent feature enables\n(and independent SPIR-V capabilities) so implementations can adopt them\nincrementally (or they could be promoted incrementally) if needed. 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