VkGpaPerfBlockAMD

typedef enum VkGpaPerfBlockAMD {
    VK_GPA_PERF_BLOCK_CPF_AMD = 0,
    VK_GPA_PERF_BLOCK_IA_AMD = 1,
    VK_GPA_PERF_BLOCK_VGT_AMD = 2,
    VK_GPA_PERF_BLOCK_PA_AMD = 3,
    VK_GPA_PERF_BLOCK_SC_AMD = 4,
    VK_GPA_PERF_BLOCK_SPI_AMD = 5,
    VK_GPA_PERF_BLOCK_SQ_AMD = 6,
    VK_GPA_PERF_BLOCK_SX_AMD = 7,
    VK_GPA_PERF_BLOCK_TA_AMD = 8,
    VK_GPA_PERF_BLOCK_TD_AMD = 9,
    VK_GPA_PERF_BLOCK_TCP_AMD = 10,
    VK_GPA_PERF_BLOCK_TCC_AMD = 11,
    VK_GPA_PERF_BLOCK_TCA_AMD = 12,
    VK_GPA_PERF_BLOCK_DB_AMD = 13,
    VK_GPA_PERF_BLOCK_CB_AMD = 14,
    VK_GPA_PERF_BLOCK_GDS_AMD = 15,
    VK_GPA_PERF_BLOCK_SRBM_AMD = 16,
    VK_GPA_PERF_BLOCK_GRBM_AMD = 17,
    VK_GPA_PERF_BLOCK_GRBM_SE_AMD = 18,
    VK_GPA_PERF_BLOCK_RLC_AMD = 19,
    VK_GPA_PERF_BLOCK_DMA_AMD = 20,
    VK_GPA_PERF_BLOCK_MC_AMD = 21,
    VK_GPA_PERF_BLOCK_CPG_AMD = 22,
    VK_GPA_PERF_BLOCK_CPC_AMD = 23,
    VK_GPA_PERF_BLOCK_WD_AMD = 24,
    VK_GPA_PERF_BLOCK_TCS_AMD = 25,
    VK_GPA_PERF_BLOCK_ATC_AMD = 26,
    VK_GPA_PERF_BLOCK_ATC_L2_AMD = 27,
    VK_GPA_PERF_BLOCK_MC_VM_L2_AMD = 28,
    VK_GPA_PERF_BLOCK_EA_AMD = 29,
    VK_GPA_PERF_BLOCK_RPB_AMD = 30,
    VK_GPA_PERF_BLOCK_RMI_AMD = 31,
    VK_GPA_PERF_BLOCK_UMCCH_AMD = 32,
    VK_GPA_PERF_BLOCK_GE_AMD = 33,
    VK_GPA_PERF_BLOCK_GL1A_AMD = 34,
    VK_GPA_PERF_BLOCK_GL1C_AMD = 35,
    VK_GPA_PERF_BLOCK_GL1CG_AMD = 36,
    VK_GPA_PERF_BLOCK_GL2A_AMD = 37,
    VK_GPA_PERF_BLOCK_GL2C_AMD = 38,
    VK_GPA_PERF_BLOCK_CHA_AMD = 39,
    VK_GPA_PERF_BLOCK_CHC_AMD = 40,
    VK_GPA_PERF_BLOCK_CHCG_AMD = 41,
    VK_GPA_PERF_BLOCK_GUS_AMD = 42,
    VK_GPA_PERF_BLOCK_GCR_AMD = 43,
    VK_GPA_PERF_BLOCK_PH_AMD = 44,
    VK_GPA_PERF_BLOCK_UTCL1_AMD = 45,
    VK_GPA_PERF_BLOCK_GE1_AMD = VK_GPA_PERF_BLOCK_GE_AMD,
    VK_GPA_PERF_BLOCK_GE_DIST_AMD = 46,
    VK_GPA_PERF_BLOCK_GE_SE_AMD = 47,
    VK_GPA_PERF_BLOCK_DF_MALL_AMD = 48,
    VK_GPA_PERF_BLOCK_SQ_WGP_AMD = 49,
    VK_GPA_PERF_BLOCK_PC_AMD = 50,
    VK_GPA_PERF_BLOCK_GL1XA_AMD = 51,
    VK_GPA_PERF_BLOCK_GL1XC_AMD = 52,
    VK_GPA_PERF_BLOCK_WGS_AMD = 53,
    VK_GPA_PERF_BLOCK_EACPWD_AMD = 54,
    VK_GPA_PERF_BLOCK_EASE_AMD = 55,
    VK_GPA_PERF_BLOCK_RLCUSER_AMD = 56,
    VK_GPA_PERF_BLOCK_RLCLOCAL_AMD = VK_GPA_PERF_BLOCK_RLCUSER_AMD,
} VkGpaPerfBlockAMD;

pub struct GpaPerfBlockAMD(u32);
impl GpaPerfBlockAMD {
    pub const CPF: Self = 0;
    pub const IA: Self = 1;
    pub const VGT: Self = 2;
    pub const PA: Self = 3;
    pub const SC: Self = 4;
    pub const SPI: Self = 5;
    pub const SQ: Self = 6;
    pub const SX: Self = 7;
    pub const TA: Self = 8;
    pub const TD: Self = 9;
    pub const TCP: Self = 10;
    pub const TCC: Self = 11;
    pub const TCA: Self = 12;
    pub const DB: Self = 13;
    pub const CB: Self = 14;
    pub const GDS: Self = 15;
    pub const SRBM: Self = 16;
    pub const GRBM: Self = 17;
    pub const GRBM_SE: Self = 18;
    pub const RLC: Self = 19;
    pub const DMA: Self = 20;
    pub const MC: Self = 21;
    pub const CPG: Self = 22;
    pub const CPC: Self = 23;
    pub const WD: Self = 24;
    pub const TCS: Self = 25;
    pub const ATC: Self = 26;
    pub const ATC_L2: Self = 27;
    pub const MC_VM_L2: Self = 28;
    pub const EA: Self = 29;
    pub const RPB: Self = 30;
    pub const RMI: Self = 31;
    pub const UMCCH: Self = 32;
    pub const GE: Self = 33;
    pub const GL1A: Self = 34;
    pub const GL1C: Self = 35;
    pub const GL1CG: Self = 36;
    pub const GL2A: Self = 37;
    pub const GL2C: Self = 38;
    pub const CHA: Self = 39;
    pub const CHC: Self = 40;
    pub const CHCG: Self = 41;
    pub const GUS: Self = 42;
    pub const GCR: Self = 43;
    pub const PH: Self = 44;
    pub const UTCL1: Self = 45;
    pub const GE1: Self = Self::GE;
    pub const GE_DIST: Self = 46;
    pub const GE_SE: Self = 47;
    pub const DF_MALL: Self = 48;
    pub const SQ_WGP: Self = 49;
    pub const PC: Self = 50;
    pub const GL1XA: Self = 51;
    pub const GL1XC: Self = 52;
    pub const WGS: Self = 53;
    pub const EACPWD: Self = 54;
    pub const EASE: Self = 55;
    pub const RLCUSER: Self = 56;
    pub const RLCLOCAL: Self = Self::RLCUSER;
}